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Date de création : 21.03.2011
Dernière mise à jour : 16.06.2016
712 articles


IAP technology based on single chip LED display

Publié le 11/05/2011 à 05:30 par eraled Tags : LED display control system article tube mode

IAP technology based on single chip LED display control system

The LED display since it has less consumption, long service life, low cost, high brightness, low malfunction, perspective, visible distance wait for a characteristic, has become a new generation of information transmission media tools. Compared with LCD LED the most outstanding characteristic is, high brightness, low cost and screen size according to the situation PinZhi with standard LED unit board. According to installation location can be divided into outdoor, half outdoor and indoor; The color can be divided into monochrome, double colors and color; Press leds point distance can be divided into phi 5.0, phi 3.75 and phi 3.0, etc. Based on the common indoor double color on the market for the control object LED unit board, explains the IAP technology based on single chip LED display control system working principle and data organization methods.

1 bi-color LED unit board hardware composition and working principle

Common indoor bi-color LED unit plate circuit diagram as shown in figure 1 (a) below. By scanning circuit 2 slices of 74HC138 (3-8 decoder) consisting of four - 16 decoder plus multiple 4953 (MOS tube), composed of scanning mode for 1/16. Fluctuation half screen by 2 groups respectively with 74HC595 serial shift register realize red, green display data input, in figure 1 list shown (a) the 64 x 32 standard LED unit, each group plate serial det shift register 74HC595 eight of cascade, four groups share the 32 74HC595. 74HC595 internal circuit diagram is shown in figure 1 (b) below. All four groups 74HC595 control signals SCK, EN RCK, all connected together with. 74HC595 control signals and four groups serial shift register input and scanning control signal A, B, C, D constitute the whole LED unit board input; The control signal 74HC595 by driving and after four groups serial det shift register and row after the output of driven scanning control signal A, B, c, D constitute the whole LED unit of output, used for board cascade next LED unit board input. Bi-color LED unit board equivalent circuit diagram as shown in figure 1 (c) below.

2 LED display control system hardware composition and working principle

The LED display and control systems hardware shown in figure 2. On the surface is a common microcontroller simple application in design, in fact, the system has considered a lot of hardware, software and hardware or software cooperate factors. First in use, under the precondition of 51 single-chip microcomputer with its serial port mode 0 can seem a microcontroller shift pulse will 8 bits of data into 74HC595, but to achieve figure 2 8 bits of data input at the same time must add the other auxiliary chip, and in shorten data transmission time do no good. Secondly, based on FPGA, CPLD etc programmable chips into dedicated hardware circuit design with single-chip microcomputer interface can be increased greatly the speed of data transmission, but also costs will synchronize greatly improved.

 

3 LED display control system of data organization and software optimization

The LED display and control system of data organization fig.03 shows. From graph 2 can get figure 3 (a) shows look from the front in the past with display data bits display lines and colors of corresponding relation. In order to improve the data reading speed, will display the data in scan line of continuous arrangement, can get figure 3 (b) shows the storage unit and scan line, storage unit data bits, and color relations.

 

According to the following specific when programming steps: (1) will be ready to scan line address the low send P2 mouth four. (2) will display lines DPTR pointing to the corresponding storage unit first address. By comparing for pointer, use "DPTR MOXCA, A + DPTR" @ read display data, and will display the data sent P0 mouth. (4) P3.6 SCK, also produced by DPTR add 1. (5), (3), (4) repeat (2) until a line data shows finished, through RCK will P3.4 produced by the shift register immigrating line of figures show. 6. Repeat (2), (3), (4), (5) until 15 rows all show ended. Repeated 1 ~ 6 refresh behaved display.

According to the above programming steps, can easily make a show the first I done subroutines 1. Subroutines 1 first 3 step to the 9th behavior cycle body, send 1 byte of the display data to 10 machine cycle of bytes, machine code for 11. Through the analysis for the rising edge of 74HC595 SCK, usable MCU write effective signal (WR) to replace, so subroutines 1 of article 5, 6, 7 line 3 instructions available "MOVX @ R0, A" instruction to replace, experiments show the replacement is reliable. Show the first I done subroutines 2 for replacement procedures, send 1 bytes of display data reduced to nine needed machine cycle of bytes, opcode reduced to 6. First I done again to show subroutine 2 careful analysis, found that in use only after SST89E516 internal 64 KB Flash memory as display data storage and not increase auxiliary circuit premise, only subroutines 2 line 7 "DJNZ R0 DP1" this article, two machine cycle 2 bytes instructions, can use SST89E516 internal 64 KB Flash memory of the characteristics of big, direct simply repeating the program in the first 2 256 3, 4, 5, and 6 do four single-byte instructions, which can shorten the time of 2 machine cycle. So send 1 bytes of machine cycle can reduce for 7, but programs need to add 1 KB. The Flash memory to 64 KB, program for not much 1KB reduce increased display data. Compared with subroutines 1, subroutines 3 speed increased by 30%. In figure 2 shows 12 MHz SST89E516 crystals and use the 2x function, its a machine cycle for 0.5 muon s, ignoring other data processing time in the premise, display 1 screen time needed for complete data which is (7 x 0.5 muon s x 256 column x 16 line) = 14.336 ms per second (nearly 70 frame). Experiments show that: the human eye twinkle of the LED display began to feel about 55 frame, namely every per frame time and mS. In figure 2, figure 1 (c) and 3 subroutine can see, a frame display data in main memory arrangement has the following features: (1) the order by scanning scanning lined; (2) for each line of the order by data output lined; (3) through the optimization of hardware and software to each display data output the shortest time.