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Par ztlights, le 14.09.2011
· The LED display principle
· electronic led display problems and solutions
· A practical LED screens display circuit design
· LED Tube-in production by ERALIGHT in shenzhen china
· LED Lamp built-in fan cooling technology is introduced
· LED display structure
· led llighting power factor correction
· The future development trend of led display technology
· A based on CPLD LED display control
· The LED display preventive maintenance
· LED display common fault handling methods
· Calculating the LED display screen body
· IAP technology based on single chip LED display
· How to distinguish the LED display grades of discretion
· The top salesman led display 15 winning strategy
Date de création : 21.03.2011
Dernière mise à jour :
16.06.2016
712 articles
A based on CPLD LED display control circuit of the solution
LED electronic display technology development is rapid, has become the flat led panel display in the field of one of the leading. This paper introduces the use M4A5-128 P64-10 VC design led display control circuit.
1 the led display of the form
In LED display system, dot matrix structure for the basic unit formed. Each show drive unit is 8 x 8 a number of dot matrix LED display screen module. Through the DuoGe display driver board assembled together, form a number that can be used to display the square meters show various text, images. The led display including computer video acquisition circuit and control circuit, drive circuit and power supply, as shown in figure 1 below.
The led display with red, green two gezer, each gezer level 256, pixel grayscale pitch of 7.62 mm, pixel in a horizontal direction can be reached 1024 points, vertical direction can be reached 768 points.
2 LED electronic display characteristics
The led display is by several display unit joining together, the display of a way of led dot matrix and the computer monitor screen phase mapping principle, namely of led dot matrix of a pixel corresponds to the computer display a pixel, such as the images on the computer screen according to the resolution is divided into 640, 480 line, that is listed on the led display 640 x 480 dot matrix unit, each dot matrix unit and include red, green, blue three light-emitting diodes that these three leds issued three kinds of color of light mixed color to get the human eye feel, color according to optical three colors principle, we only collection on the computer screen every bit of digital image and into red, green and blue three kinds of signal systems, after treatment, a transfer to of led dot matrix on the screen of dot matrix unit, which is driven color corresponding light-emitting diodes (leds), that is, realizing the computer screen in of led dot matrix screen mapping.
3 LED electronic display driver principle
In most LED display screen system, are adopted the refresh type driving method, that is, each LED display drive unit to lock up data column, thus to scanned, according to the LED display driver board structure, using 1 P16 scanning duly ratio.
We design the led sign driver drive circuit board with two pieces of 74 HC595 are needed no line of decoder, it provides the whole scanning circuit needed row signal, and also use 74 HC595 are needed for the chip to serial shift register, it will be from the system serial data shift into parallel signal output, so drive column need to provide serial shift clock, parallel lock into the signal and output make can signal, serial data input and scanning need serial shift the clock signal, as shown in figure 2 shows. So we need to design a sequential control circuit.
4 the
--128 M4A5 P64-10 VC Lattice is the production of CPLD device, there are 128 units, 64 macro IPO pins. Company development software ispDesignEXPERT Lattice in the design of integrated, compilation, input validation and programming all work. First of all, can direct input to carry on the design drawing principle diagram, also can use VHDL language programming. We need from 10 MHz clock get 100 KHz signal source with VHDL language in VHDLMODULE text editor, write a document called F100K. HDL are as follows:
The design documents compiled, and then after the input user can adjust the tube feet distribution, compile through, can on chip programming. With an uploaded file download the Blaster-cable computer parallel port and on the PCB JTAG socket connection up, after electrify the installed good chip programming.
Practice shows that in the production of Lattice M4A5-128 P64-10 of the circuit design VC meet the design requirements.